1. Field of the Invention
The present invention relates to a phase locked loop circuit, and particularly relates to a multi-loop phase locked loop circuit.
2. Description of the Prior Art
In circuit fields, a phase locked loop circuit is used for providing different frequencies to different signals. Please refer to FIG. 1. FIG. 1 is a block diagram illustrating a prior art PLL (phase locked loop) circuit 100. The PLL 100 comprises a phase/frequency detector 102, a charge pump 104, a loop filter 106 and a voltage-controlled oscillator 108. The phase/frequency detector 102 is used for comparing the difference between a reference clock signal RCS and a feed back clock signal FCS and generates a difference signal DS accordingly, wherein the value of the difference signal DS is directly proportional to the phase/frequency difference between the reference clock signal RCS and the feed back clock signal FCS. The charge pump 104 generates a control current Ic to the loop filter 106 according to the difference signal DS. The charge pump 104 provides a current Isource to the loop filter 106 if the difference signal DS is UP and the charge pump 104 sinks a current Isink from the loop filter 106 if the difference signal DS is DOWN, wherein the Isource is equal to Isink. The loop filter 106 suppresses the high frequency component of the control current Ic and outputs a control signal CS for controlling the voltage-controlled oscillator 108. The output of the voltage-controlled oscillator 108 is utilized as an oscillating signal OS and is frequency-divided by the frequency-divider 110 to form a feed-back clock signal FCS. In this way, the oscillating signal OS will be gradually locked to the reference clock signal RCS.
The processing speed of the electronic apparatus increases as technology improves, however. The speed of the above-mentioned prior art PLL is limited, such that the demand of high frequency jumping system such as UWB (Ultra Wideband) cannot be met. Therefore, a PLL with faster convergence speed is needed.